As semiconductor devices continue to be scaled down, the area of a memory cell becomes smaller. Although the memory cell is smaller, capacitor area has not been reduced because of a need to maintain appropriate levels of capacitance. For example, a unit cell needs an appropriate charge capacitance for durability against the soft error caused by α-particles and a sensing signal margin.
A number of alternatives for maintaining a capacitance of a memory capacitor beyond a predetermined value are known. In accordance with the equation C=∈As/d (C being a capacitance, ∈ being a dielectric constant, As being a surface area of an electrode, and d being a thickness of a dielectric film), a first approach has been to reduce the surface area of a dielectric film (d). A second approach has been to increase the surface area of an electrode (As), and a third approach has been to use a material having a high dielectric constant (∈).
A problem with the first approach is that as the thickness of a dielectric film is reduced, leakage current increases. As a result, the second and third approaches have been used more often than the first. In the second approach, when the surface area of an electrode is increased, a capacitor structure is transformed into a three dimensional (3D) structure such as, for example, a simple stack structure, a concave structure, a cylindrical structure, and a multi-fin structure. The third approach uses a material with a high dielectric constant such as, for example, (Ba,Sr)TiO3(BST), (Pb,Zr)TiO3(PZT), and Ta2O5.
As a result of the second approach, a capacitor having a cylindrical (or concave) structure has been suggested to overcome a difficulty in etching a lower electrode as the height of a 3-dimensionally stacked capacitor increases.
A semiconductor device with a conventional concave-type capacitor is now described below with reference to FIG. 1 in which reference numerals 70 and 80 denote a cell region and a peripheral circuit region, respectively.
Referring to FIG. 1, in the cell region 70 and peripheral circuit region 80, a MOS transistor is disposed on a substrate 2 where a device isolation region 4 is formed. The MOS transistor has a gate electrode 11 and a source/drain region 18. The gate electrode 11 has a polysilicon layer 8 and a silicide layer 10 formed on a gate insulating layer 6. A spacer 14 is formed on sidewalls of the gate electrode 11. The source/drain region 18 includes a lightly doped region 12 and a heavily doped region 16.
A first interlayer dielectric 20 is stacked on the substrate 2 including the MOS transistor. Contacts 26a, 26b, and 26c are connected to the source/drain region 18 of the MOS transistor through the first interlayer dielectric 20. A contact 26d is coupled to the gate electrode 11. Each of the contacts 26a, 26b, 26c, and 26d includes barrier metal 22 and a tungsten layer 24.
A second interlayer dielectric 28 is stacked on a first interlayer dielectric 20 including the contacts 26a, 26b, 26c, and 26d. In the cell region 70, a concave hole 29 is formed to expose the contact 26a through the second interlayer dielectric 28. A capacitor 36 coupled to the contact 26a is disposed in the concave hole 29. The capacitor 36 consists of a lower electrode 30, a dielectric film 32, and an upper electrode 34.
In the cell region 70, a third interlayer dielectric 40 is stacked on the second interlayer dielectric 28 including the capacitor 36. In the peripheral circuit region 80, a second interlayer dielectric 28 and a third interlayer dielectric 40 are sequentially stacked.
In the cell region 70, a contact 46a is electrically connected to the upper electrode 34 of the capacitor 36 through the third interlayer dielectric 40. The contact 46a is coupled to an interconnection 52a. A bitline contact 46b is electrically connected to the contact 26b through the third interlayer dielectric 40 and the second interlayer dielectric 28. The bitline contact 46b is coupled to a bitline 52b. In the peripheral circuit region 80, contacts 46c and 46d are formed to be electrically connected to the contacts 26c and 26d through the third interlayer dielectric 40 and the second interlayer dielectric 28. The contacts 46c and 46d are coupled to interconnections 52c and 52d, respectively. The contacts 46a, 46b, 46c and 46d consist of barrier metal 42 and a tungsten layer 44. The bitline 52b includes barrier metal 48 and a conductive layer 50. Similarly, each of the interconnections 52a, 52c, and 52d includes barrier metal 48 and a conductive layer 50.
In a semiconductor device having a concave-type (or cylindrical) capacitor in a capacitor under bitline (CUB) structure, the contacts 46a, 46b, 46c, and 46d may be formed by the following method: the third interlayer 40 dielectric is etched to form an opening 41a exposing a surface of the upper electrode 34, and the third interlayer dielectric 40 and the second dielectric 28 are successively etched to form openings 41b exposing the contacts 26b, 26c, and 26d. 
Since the openings 41b exposing the contacts 26b, 26c, and 26d are deeper than the opening 41a exposing the upper electrode 34, the upper electrode 34 may be overetched. Accordingly, there is a need for a method of rapidly forming a thick upper electrode in order to enhance a yield.
In addition, data stored in a dynamic random access memory (DRAM) cell is maintained as an amount of charge stored in a capacitor and is retained by means of regular refresh operations. To normally operate DRAM, the stored charges must not be lost during the refresh operations. Accordingly, there is a need for a capacitor which eliminates leakage current.